1. Field of the Invention
The present invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure having protruding elements formed on a circuit layer thereof and a method for fabricating the package structure.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. To meet the high integration and miniaturization requirements of package structures, conductive pads of circuit layers of the package structures are continuously reduced in size.
Generally, a semiconductor chip is disposed on the conductive pads of a circuit layer through a plurality of conductive bumps. However, during a reflow process, the conductive bumps easily collapse and overflow, which adversely affects the electrical connection quality and even causes a short circuit to occur between adjacent conductive bumps. Further, the contact area between the conductive pads and the conductive bumps is quite small due to planar contact surfaces of the conductive pads, thus leading to a poor bonding between the conductive pads and the conductive bumps and consequently reducing the product reliability.
FIGS. 1A to 1D are schematic cross-sectional views showing a package structure 1 and a fabrication method thereof according to the prior art.
Referring to FIG. 1A, a carrier 10 is provided, and a circuit layer 11 having a plurality of conductive pads 111 is formed on the carrier 10.
Referring to FIG. 1B, a first encapsulant 12 is formed on the carrier 10 to encapsulate the circuit layer 11. The first encapsulant 12 has a first surface 12a and a second surface 12b opposite to the first surface 12a and facing the carrier 10.
Referring to FIG. 1C, the overall structure of FIG. 1B is turned upside down and the carrier 10 is removed. Then, a chip 13 is disposed on the conductive pads 111 of the circuit layer 11 through a plurality of conductive bumps 14.
Referring to FIG. 1D, a second encapsulant 15 is formed on the second surface 12b of the first encapsulant 12 to encapsulate the circuit layer 11, the chip 13 and the conductive bumps 14. Further, a plurality of openings 121 are formed on the first surface 12a of the first encapsulant 12 to expose portions of the circuit layer 11, and a plurality of solder balls 16 are formed in the openings 121 and electrically connected to the circuit layer 11. As such, a package structure 1 is obtained.
However, the package structure 1 has several drawbacks. During a reflow process, the conductive bumps 14 easily collapse and the conductive material (for example, solder material) of the conductive bumps 14 easily overflows, thus adversely affecting the electrical connection quality and even causing a short circuit to occur between adjacent conductive bumps 14. Further, planar contact surfaces 112 of the conductive pads 111 result in a small contact area between the conductive pads 111 and the conductive bumps 14, thus leading to a poor bonding between the conductive bumps 14 and the circuit layer 11 and consequently reducing the product reliability.
Therefore, there is a need to provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks.